HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 593

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by
the SCI in receive mode and transmit mode as described below.
• Retransfer operation when SCI is in receive mode
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
Note: * The DTC is not implemented in the H8S/2635 Group.
• Retransfer operation when SCI is in transmit mode
[6] If an error signal is sent back from the receiving end after transmission of one frame is
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode.
automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
If DTC * data transfer by an RXI source is enabled, the contents of RDR can be read
automatically. When the RDR data is read by the DTC * , the RDRF flag is automatically
cleared to 0.
error signal transmission.
Figure 14-12 illustrates the retransfer operation when the SCI is in transmit mode.
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
RDRF
PER
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 14-11 Retransfer Operation in SCI Receive Mode
nth transfer frame
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransferred frame
(DE)
[4]
[3]
Section 14 Smart Card Interface
Ds D0 D1 D2 D3 D4
Transfer
frame n + 1
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