HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 609

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
15.2.5
ICCR is an 8-bit readable/writable register that enables or disables the I
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
acknowledgement, confirms the I
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—I
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the I
internal states are cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
Bit 7
ICE
0
1
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value :
R/W
Note: * Only 0 can be written, for flag clearing.
2
C Bus Interface Enable (ICE): Selects whether or not the I
I
2
C Bus Control Register (ICCR)
Description
I
I
SAR and SARX can be accessed
I
driving the bus)
ICMR and ICDR can be accessed
2
2
2
C bus interface module disabled, with SCL and SDA signal pins set to port function
C bus interface module internal states initialized
C bus interface module enabled for transfer operations (pins SCL and SCA are
:
:
R/W
ICE
7
0
IEIC
R/W
6
0
2
C bus interface bus status, issues start/stop conditions, and
MST
R/W
5
0
TRS
R/W
4
0
2
C bus interface module is halted and its
ACKE
(Only for the H8S/2638, H8S/2639, and H8S/2630)
R/W
3
0
BBSY
Section 15 I
R/W
2
C bus interface is to be
2
0
2
C bus interface, enables or
R/(W)*
2
IRIC
C Bus Interface [Option]
1
0
(Initial value)
Page 559 of 1458
SCP
W
0
1