HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 616

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Table 15-3 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL
1/0
1
1
1
1
0
0
0
0
0
0
0
0
Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not stored.
Bit 0
SCP
0
1
Page 566 of 1458
1/0
1
1
1/0
1/0
0
0
0
0
1/0
1/0
1
1/0
2
C Bus Interface [Option]
Writing 0 issues a start or stop condition, in combination with the BBSY flag
Reading always returns a value of 1
Writing is ignored
Description
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1/0
0
0
0
0
0
0
0
0
0
0
0
0
1/0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1/0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
AAS ADZ
0
0
0
0
0
1/0
1
1
0
0
0
0
0
0
0
0
0
0
1/0
0
1
0
0
0
0
0
0
0
0
0/1
0/1
0
0
0
0
0/1
0
1
0/1
ACKB State
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
Start condition
Start condition
Arbitration lost
SAR match by first
SARX match
Idle state (flag
clearing required)
issuance
established
Master mode wait
Master mode
transmit/receive end
frame in slave mode
General call
address match
Slave mode
transmit/receive end
(except after SARX
match)
Slave mode
transmit/receive end
(after SARX match)
Stop condition
detected
(Initial value)
May 28, 2010