HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 619

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 5
IRTR
0
1
Bit 4—Second Slave Address Recognition Flag (AASX): In I
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX
0
1
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Description
Waiting for transfer, or transfer in progress
[Clearing conditions]
Continuous transfer state
[Setting conditions]
Description
Second slave address not recognized
[Clearing conditions]
Second slave address recognized
[Setting condition]
When 0 is written in IRTR after reading IRTR = 1
When the IRIC flag is cleared to 0
In I
When the TDRE or RDRF flag is set to 1 when AASX = 1
In other modes
When the TDRE or RDRF flag is set to 1
When 0 is written in AASX after reading AASX = 1
When a start condition is detected
In master mode
When the second slave address is detected in slave receive mode and FSX = 0
2
C bus interface slave mode
(Only for the H8S/2638, H8S/2639, and H8S/2630)
2
C bus format slave receive mode,
Section 15 I
2
C Bus Interface [Option]
(Initial value)
(Initial value)
Page 569 of 1458

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