HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 633

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Figure 15-10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
No
No
No
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
1 clock cycle wait state
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Set WAIT = 1 (ICMR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Write BBSY = 0
Final receive?
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRTR = 1?
IRIC = 1?
IRIC = 1?
End
Yes
Yes
Yes
No
No
Yes
Yes
(Example)
[1] Set to receive mode
[2] Receive start, dummy read
[3] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[4] Data receive completed judgment
[5] Read receive data
[6] Clear IRIC flag (cancel wait state)
[7] Set acknowledge data for final receive
[8] Wait time until TRS setting
[9] Set TRS to generate stop condition
[10] Read receive data
[11] Clear IRIC flag (cancel wait state)
[12] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[13] Data receive completed judgment
[14] Clear IRIC flag (cancel wait state)
[15] Cancel wait mode
[16] Read final receive data
[17] Generate stop condition
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle)
Clear IRIC flag (IRIC flag should be cleared when WAIT = 0)
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Section 15 I
2
C Bus Interface [Option]
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