HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 636

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
[14] If the IRTR flag value is 0, clear the IRIC flag to 0 to cancel the wait state. Return to reading
[15] Clear the WAIT bit in ICMR to 0 to cancel the wait mode. Then clear the IRIC flag to 0. The
[16] Read the final receive data in ICDR.
[17] Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
Page 586 of 1458
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
Master transmit mode
receive operation has finished, perform the issue stop condition processing described in step
[15] below.
the IRIC flag, as described in step [12], to detect the end of the receive operation.
IRIC flag should be cleared when the value of WAIT is 0 (The stop condition may not be
output properly when the issue stop condition instruction is executed if the WAIT bit was
cleared to 0 after the IRIC flag is cleared to 0).
and generates the stop condition.
2
C Bus Interface [Option]
Figure 15-12 Example of Master Receive Mode Operation Timing
A
9
[1] TRS cleared to 0
IRIC clearance
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
[2] ICDR read (dummy read)
Master receive mode
1
2
(MLS = ACKB = 0, WAIT = 1)
3
Data 1
4
5
Bit 2 Bit 1 Bit 0
6
7
[6] IRIC clearance
8
(cancel wait)
[4] IRTR = 0
[3]
A
[3]
[4] IRTR = 1
9
[5] ICDR read
H8S/2639, H8S/2638, H8S/2636,
(data 1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Data 1
1
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
2
Data 2
[6] IRIC clearance
3
May 28, 2010
4
5

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