HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 657

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• Notes on TRS Bit Setting in Slave Mode
REJ09B0103-0800 Rev. 8.00
May 28, 2010
SDA
SCL
TRS
From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the
rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 15-26)
in the slave mode of the I
effective immediately.
However, at other times (indicated as (b) in figure 15-26) the value set in the TRS bit is put on
hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than
taking effect immediately.
This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no
acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an
address receive operation following a restart condition input with no stop condition
intervening.
When receiving an address in the slave mode, clear the TRS bit to 0 during the period
indicated as (a) in figure 15-26.
To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS
bit to 0 and then perform a dummy read of the ICDR register.
Data transmission
8
Detection of 9th clock
cycle rising edge
9
TRS bit set
(a)
Figure 15-26 TRS Bit Setting Timing in Slave Mode
ICDR dummy read
Restart condition
2
C bus interface, the value set in the TRS bit in the ICCR register is
1
TRS bit setting hold time
2
Address reception
3
(b)
4
(Only for the H8S/2638, H8S/2639, and H8S/2630)
5
6
Section 15 I
7
Detection of 9th clock
cycle rising edge
8
2
C Bus Interface [Option]
A
9
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