HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 659

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• Notes on Wait Operation in Master Mode
REJ09B0103-0800 Rev. 8.00
May 28, 2010
(Master transmit mode)
(Master transmit mode)
(Slave receive mode)
Though it is prohibited in the normal I
MST bit is erroneously set to 1 and a transition to master mode is occurred during data
transmission or reception in slave mode. In multi-master mode, pay attention to the setting of
the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register
should be set to 1 according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
(b) Set the MST bit to 1.
(c) To confirm that the bus was not entered to the busy state while the MST bit is being set,
During master mode operation using the wait function, when the interrupt flag IRIC bit is
cleared from 1 to 0 between the falling edge of the 7th clock cycle and the falling edge of the
8th clock cycle, in some cases no wait is inserted after the falling edge of the 8th clock cycle
and the clock pulse of the 9th clock cycle is output continuously.
Observe the following with regard to clearing the IRIC flag while using the wait function.
At the rising edge of the 9th clock cycle, set the IRIC flag to 1 and then clear it to zero before
the rising edge of the 1st clock cycle (while the value of the BC2 to BC0 counter value is 2 or
greater).
If clearing of the IRIC flag is delayed by interrupt processing or the like and the BC counter
value reaches 1 or 0, confirm that the SCL pin state is low-level after the BC2 to BC0 counter
has reached 0 and then clear the IRIC flag. (See figure 15.28.)
I
I
2
2
C bus interface
C bus interface
Other device
the MST bit.
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Figure 15-27 Diagram of Erroneous Operation when Arbitration is Lost
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
A
A
A
2
C protocol, the same problem may occur when the
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as an
• When the receive data matches to
receive mode
address
the address set in the SAR or SARX
register, the I
as a slave device.
SLA
DATA1
DATA2
2
(Only for the H8S/2638, H8S/2639, and H8S/2630)
C bus interface operates
Transmit data does not match
R/W
A
A
Section 15 I
2
DATA4
DATA3
C Bus Interface [Option]
Data contention
Page 609 of 1458
A
A

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