HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 689

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception
interrupt requests.
Bit 9: IMR1
0
1
Bit 8—Reserved: The reset flag cannot be masked. This bit always reads 0. The write value
should always be 0.
Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.
Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to
bus operation in sleep mode.
Bit 4: IMR12
0
1
Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite
interrupt requests.
Bit 1: IMR9
0
1
Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt
requests.
Bit 0: IMR8
0
1
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Description
Message reception interrupt request (RM1) to CPU by IRR1 enabled
Message reception interrupt request (RM1) to CPU by IRR1 disabled
Description
Bus operation interrupt request (OVR0) to CPU by IRR12 enabled
Bus operation interrupt request (OVR0) to CPU by IRR12 disabled
Description
Unread message overwrite interrupt request (OVR0) to CPU by IRR9
enabled
Unread message overwrite interrupt request (OVR0) to CPU by IRR9
disabled
Description
Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled
Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled
Section 16 Controller Area Network (HCAN)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Page 639 of 1458

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