HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 722

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is
delayed until the bus becomes idle.
Either of the following methods of clearing HCAN sleep mode can be selected by making a setting
in the MCR7 bit.
1. Clearing by software
2. Clearing by CAN bus operation
Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus
communication is enabled again.
Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the
CAN bus performs an operation and this change is detected. In this case, the first message is not
received in the mailbox, and normal reception starts from the next message. When a change is
detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in
the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR)
is set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
Page 672 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010

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