HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 729

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
(10) HCAN Transmit Procedure
When transmission is set while the bus is in the idle state, if the next transmission is set or the set
transmission is canceled under the following conditions within 50 μs, the transmit message ID of
being set may be damaged.
• When the second transmission has the message whose priority is higher than the first one
• When the massage of the highest priority is canceled in the first transmission
Make whichever setting shown below to avoid the message IDs from being damaged.
• Set transmission in one TXPR. After transmission of all transmit messages is completed, set
• Make the transmission setting according to the priority of transmit messages.
• Set the interval to be 50 μs or longer between TXPR and another TXPR or between TXPR and
Table 16-6 Interval Limitation between TXPR and TXPR or between TXPR and TXCR
Baud Rate (bps)
1 M
500 k
250 k
(11) Note on Releasing the HCAN Reset or HCAN Sleep
Before releasing the HCAN reset or HCAN sleep (MCR0 = 0 or MCR5 = 0), confirm that the
GSR3 bit (the reset status bit) is set to 1.
(12) Note on Accessing Mailbox during the HCAN Sleep
Do not access the mailbox during the HCAN sleep. If accessed, the CPU might halt. Accessing
registers during the HCAN sleep does not cause the CPU halt, nor does accessing the mailbox in
other than the HCAN sleep mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
transmission again (mass transmission setting). The interval between transmission settings
should be 50 μs or longer.
TXCR.
⎯ Reset the HCAN during the bus-off period to clear the messages in the mailboxes
[Countermeasure]
waiting for transmission. To reset the HCAN, set the module stop bit (MSTPC3 in
MSTPCRC) to 1 and then clear it. In this case, the HCAN is entirely reset. Therefore
the initial settings must be made again.
Set Interval (μs)
50
50
50
Section 16 Controller Area Network (HCAN)
Page 679 of 1458