HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 819

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• Before branching to the programming control program (RAM area H'FFE800), the chip
• Boot mode can be entered by making the pin settings shown in table 21A-9 and executing a
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (t
21A.8.2 User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means of FWE control and supply of
programming data, and storing a program/erase control program in part of the program area as
necessary.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE
and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data
output pin, TxD1, goes to the high-level output state (P33DDR = 1, P33DR = 1).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
reset-start.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
the FWE pin and mode pins, and executing reset release *
WDT overflow reset.
Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low *
while the boot program is being executed or while flash memory is being programmed or
erased.
state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)
will change according to the change in the microcomputer’s operating mode *
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
2. See appendix D, Pin States.
3. For precautions on applying and disconnecting FWE, see section 21A.15, Flash
states) with respect to the reset release timing.
Memory Programming and Erasing Precautions.
1
. Boot mode can also be cleared by a
2
.
Section 21A ROM
(H8S/2636 Group)
Page 769 of 1458
MDS
3
= 4