HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 881

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21B.9.3
When erasing flash memory, the single-block erase flowchart shown in figure 21B-13 should be
followed.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of erase operations (N) are shown in section 24.2.7 and 24.3.7, Flash
Memory Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 and 2 (EBR1, EBR2) at least (t
FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway,
etc. Set a value of about 19.8 ms as the WDT overflow period. Preparation for entering erase mode
(erase setup) is performed next by setting the ESU bit in FLMCR1. The operating mode is then
switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least (t
time during which the E bit is set is the flash memory erase time. Ensure that the erase time does
not exceed (t
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
21B.9.4
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (t
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV
bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made
to the addresses to be read. The dummy write should be executed after the elapse of (t
more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least (t
read operation. If the read data has been erased (all 1), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is
completed, exit erase-verify mode, and wait for at least (t
all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (t
If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and
repeat the erase/erase-verify sequence as before.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
be erased to all 0) is not necessary before starting the erase procedure.
Erase Mode
Erase-Verify Mode
se
) ms.
sevr
) µs after the dummy write before performing this
sswe
) µs after setting the SWE bit to 1 in
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
cev
) µs. If erasure has been completed on
Section 21B ROM
sesu
Page 831 of 1458
sev
cswe
) µs. The
) µs or
) µs.
ce
) µs