HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 931

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21C.9.2
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least
(t
watchdog timer setting is also cleared. The operating mode is then switched to program-verify
mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write
of H'FF data should be made to the addresses to be read. The dummy write should be executed
after the elapse of (t
in 16-bit units), the data at the latched address is read. Wait at least (t
before performing this read operation. Next, the originally written data is compared with the verify
data, and reprogram data is computed (see figure 21C-12) and transferred to RAM. After
verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least
(t
again, and repeat the program/program-verify sequence as before. The maximum number of
repetitions of the program/program-verify sequence is indicated by the maximum programming
count (N). Leave a wait time of at least (t
Notes on Program/Program-Verify Procedure
1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must
2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer
3. Verify data is read in word units.
4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is
REJ09B0103-0800 Rev. 8.00
May 28, 2010
cp
cpv
) µs before clearing the PSU bit to exit program mode. After exiting program mode, the
be H'00 or H'80.
should be used.
128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write
H'FF data to the extra addresses.
set. In the chip, write pulses should be applied as follows in the program/program-verify
procedure to prevent voltage stress on the device and loss of write data reliability.
a. After write pulse application, perform a verify-read in program-verify mode and apply a
) µs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode
write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write
bits in the 128-byte write data are read as 0 in the verify-read operation, the
program/program-verify procedure is completed. In the chip, the number of loops in
reprogramming processing is guaranteed not to exceed the maximum value of the
maximum programming count (N).
Program-Verify Mode
spv
) µs or more. When the flash memory is read in this state (verify data is read
cswe
) µs after clearing SWE.
spvr
) µs after the dummy write
Section 21C ROM
(H8S/2635 Group)
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