HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 934

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 21C ROM
(H8S/2635 Group)
Page 884 of 1458
Note: Use a 10 μs write pulse for additional programming.
Note: 6 Write Pulse Width
Number of Writes n
Write pulse application subroutine
1000
998
999
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
10
11
12
13
Clear PSU bit in FLMCR1
1
2
3
4
5
6
7
8
9
Reprogram data storage
Additional-programming
Sub-Routine Write Pulse
Reprogram Data Computation Table
Set PSU bit in FLMCR1
Program data storage
Clear P bit in FLMCR1
Set P bit in FLMCR1
data storage area
Original Data
area (128 bytes)
area (128 bytes)
Wait (t
Wait (t
(128 bytes)
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of 30 μs or 200 μs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
7. The wait times and value of N are shown in section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics.
WDT enable
Wait (t
Wait (t
Disable WDT
(D)
RAM
End Sub
0
0
1
1
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a 10 μs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Figure 21C-12 Program/Program-Verify Flowchart
spsu
cpsu
Write Time (tsp) μsec
sp
cp
) μs
) μs
) μs
) μs
Verify Data
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
(V)
0
1
0
1
Reprogram Data
*
*
*
*
Start of programming
End of programming
5
7
7
7
*
7
(X)
Increment address
1
0
1
1
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
No
Comments
Transfer reprogram data to reprogram data area
Additional-programming data computation
Write Pulse (Additional programming)
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Wait (t
Read verify data
Wait (t
Wait (t
Wait (t
Wait (t
Yes
Yes
Write data =
verify data?
Write pulse
Yes
START
128-byte
m = 0 ?
m = 0
6
6
n = 1
sswe
cswe
spvr
Additional-Programming Data Computation Table
spv
cpv
n ?
Reprogram Data
n?
Yes
Yes
Sub-Routine-Call
Sub-Routine-Call
) μs
) μs
) μs
) μs
) μs
(X')
0
0
1
1
No
No
No
Verify Data
*
*
*
*
*
No
*
*
7
7
(V)
See Note 6 for pulse width
7
7
2
3
7
0
1
0
1
*
*
*
4
1
4
*
*
m = 1
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
4
Clear SWE bit in FLMCR1
Programming Data (Y)
Programming failure
Wait (t
Additional-
n ≥ (N)?
0
1
1
1
cswe
Yes
H8S/2639, H8S/2638, H8S/2636,
) μs
*
7
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
No
n ← n + 1
Comments
*
Reprogram
7
May 28, 2010

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