HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 147
Manufacturer Part Number
IC H8S MCU FLASH 256K 128-QFP
Renesas Electronics America
Specifications of HD64F2638F20J
CAN, SCI, SmartCard
Motor Control PWM, POR, PWM, WDT
Number Of I /o
Program Memory Size
256KB (256K x 8)
Program Memory Type
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
A/D 12x10b; D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MAC (Multiply and ACcumulate)
ERm + 2
MAC @ERn+, @ERm+
This instruction performs signed multiplication on two 16-bit operands at addresses given by the
contents of general registers ERn and ERm, adds the 32-bit product to the contents of the MAC
register, and stores the sum in the MAC register. After this operation, ERn and ERm are both
incremented by 2.
The operation can be carried out in saturating or non-saturating mode, depending on the MACS
bit in a system control register. (SYSCR)
See the relevant hardware manual for further information.
In non-saturating mode, MACH and MACL are concatenated to store a 42-bit result. The value of
bit 41 is copied into the upper 22 bits of MACH as a sign extension.
In saturating mode, only MACL is valid, and the result is limited to the range from H'80000000
(minimum value) to H'7FFFFFFF (maximum value). If the result overflows in the negative
direction, H'80000000 (the minimum value) is stored in MACL. If the result overflows in the
positive direction, H'7FFFFFFF (the maximum value) is stored in MACL. The LSB of the MACH
register indicates the status of the overflow flag (V-MULT) in the multiplier. Other bits retain
their previous contents.
This instruction is supported only by the H8S/2600 CPU.
(EAm) + MAC register
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Rev. 4.00 Feb 24, 2006 page 131 of 322
Section 2 Instruction Descriptions
Multiply and Accumulate