HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 149

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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MAC (Multiply and ACcumulate)
2. Example
CLRMAC
MAC
MAC
MAC
NOP
STMAC MACH,ER3
CLRMAC
STMAC MACH,ER3
:
Z-MULT (zero flag)
V-MULT (overflow flag)
The N-MULT, Z-MULT, and V-MULT flags are not modified by switching between
saturating and non-saturating modes, or by execution of a multiply instruction (MULXU or
MULXS).
Saturating mode
Non-saturating mode
Saturating mode
Non-saturating mode
@ER1+,@ER2+
@ER1+,@ER2+
@ER1+,@ER2+
Set when register MACL is cleared to 0 by execution of a MAC
instruction
Cleared when register MACL is not cleared to 0 by execution of a
MAC instruction
Set when registers MACH and MACL are both cleared to 0 by
execution of a MAC instruction
Cleared when register MACH or MACL is not cleared to 0 by
execution of a MAC instruction
Set when the result of the MAC instruction overflows the range
from H'80000000 (minimum) to H'7FFFFFFF (maximum)
Cleared when a CLRMAC or LDMAC instruction is executed
Note: Not cleared when the result of the MAC instruction is within
Set when the result of the MAC instruction overflows the range
from H'20000000000 (minimum) to H'1FFFFFFFFFF (maximum)
Cleared when a CLRMAC or LDMAC instruction is executed
Note: Not cleared when the result of the MAC instruction is within
the above range
the above range
Overflow occurs
Result = 0
CCR (N = 0, Z = 1, V = 1)
CCR (N = 0, Z = 1, V = 0)
Rev. 4.00 Feb 24, 2006 page 133 of 322
Section 2 Instruction Descriptions
Multiply and Accumulate
REJ09B0139-0400

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