HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 50
Manufacturer Part Number
IC H8S MCU FLASH 256K 128-QFP
Renesas Electronics America
Specifications of HD64F2638F20J
CAN, SCI, SmartCard
Motor Control PWM, POR, PWM, WDT
Number Of I /o
Program Memory Size
256KB (256K x 8)
Program Memory Type
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
A/D 12x10b; D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 1 CPU
4. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
5. Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the
absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits
long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1
(H'FFFFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute
address can access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 1.5 indicates the accessible absolute address ranges.
For further details on the accessible range, refer to the relevant microcontroller hardware manual.
Rev. 4.00 Feb 24, 2006 page 34 of 322
Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the register
value should be even.
Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word access,
or 4 for longword access. For word or longword access, the register value should be even.
Absolute Address Access Ranges
8 bits (@aa:8)
16 bits (@aa:16)
32 bits (@aa:32)
24 bits (@aa:24)
H'FF00 to H'FFFF
H'0000 to H'FFFF
H'FFFFFF00 to H'FFFFFFFF
H'00000000 to H'00007FFF,
H'FFFF8000 to H'FFFFFFFF
H'00000000 to H'FFFFFFFF
H'00000000 to H'00FFFFFF