M30878FJBGP#U5 Renesas Electronics America, M30878FJBGP#U5 Datasheet - Page 534
M30878FJBGP#U5
Manufacturer Part Number
M30878FJBGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M30878FJBGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30878FJBGP#U5M30878FJBGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 510 of 587
Table 26.5
NOTE:
26.3.5
Table 26.6
NOTES:
SR0 (b0)
SR1 (b1)
SR2 (b2)
SR3 (b3)
SR4 (b4)
SR5 (b5)
SR6 (b6)
SR7 (b7)
b7 to b0: These bits return the value of 8 low-order bits by reading an even address of the flash memory in 16-bit
Register
Status
1. The flash memory enters read array mode when the command code xxFFh is written in the second bus cycle of
2. When the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled), no error occurs under these conditions.
Bit in
1. Bits FMR07 (SR5) and FMR06 (SR4) become 0 by executing the clear status register command. When the
FMR07
If an error occurs, bits FMR07 and FMR06 in the FMR0 register become 1, indicating the occurrence of an
error. Therefore, by checking these status bits (full status check), the execution result can be confirmed.
Table 26.6 lists error types and FMR0 register values. Figure 26.13 shows a flow chart of the full status check
and handling procedure for each error.
(Status Register) values
(SR5)
FMR07 (SR5) or FMR06 (SR4) bit is 1, the program command, block erase command, lock bit program
command, and read lock bit status command cannot be accepted by the flash memory.
these commands. At the same time, the command code written in the first bus cycle is ignored.
1
1
0
FMR0 Register
units.
Full Status Check
FMR06
FMR07
Register
FMR00
FMR0
Status Register
Errors and FMR0 Register Values
Bit in
−
−
−
−
−
(1)
(1)
FMR06
(SR4)
1
0
1
Sequencer status
Program status
Status Name
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Erase status
Command sequence
error
Erase error
Program error
Error
Successfully completed
Successfully completed
BUSY
0
−
−
−
−
−
• When a command is written incorrectly
• When invalid data (data other than xxD0h or xxFFh) is
• When the block erase command is executed to a
• When the block erase command is executed to an
• When the program command is executed to a locked
• When the program command is executed to an
• The lock bit program command is executed, but the
written in the second bus cycle of the lock bit program
command or block erase command
locked block
unlocked block, but the erase operation is not
completed successfully
block
unlocked block, but the program operation is not
completed successfully
program operation is not completed successfully
(2)
Description
(2)
Error Occurrence Condition
READY
Error
Error
1
−
−
−
−
−
(1)
26. Flash Memory
Value after
Reset
−
−
−
−
0
0
−
1
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