HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 191
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708RF100A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708RF100A
Manufacturer:
HITACHI/日立
Quantity:
20 000
Part Number:
HD6417708RF100AV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bit 7—PLL Circuit Enable (PLLEN): Specifies the on/off state of PLL circuit 1. This bit is valid
in clock operating modes 3–6. PLL circuit 1 goes on when the clock operating mode is 0–2 or 7
irrespective of the value of PLLEN.
Bit 7: PLLEN
0
1
Bit 6—PLL Standby (PSTBY): Specifies PLL standby. When PLL standby is active, PLL circuit 1
will be in standby mode at the frequency specified by the STC bit. This function is valid in clock
operating modes 3–6.
Bit 6: PSTBY
0
1
Bits 5 and 4—Frequency Multiplication Ratio (STC1, STC0): These bits specify the frequency
multiplication ratio of PLL circuit 1.
Bit 5: STC1
0
0
1
1
Note: Do not set the output frequency of PLL circuit 1 higher than 60 MHz.
Bits 3 and 2—Internal Clock Frequency Division Ratio (IFC1, IFC0): These bits specify the
frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1.
When PLL circuit 1 is off or in standby mode, set 1.
Bit 3: IFC1
0
0
1
1
Note: Do not set the internal clock frequency lower than the CKIO frequency.
Bit 4: STC0
0
1
0
1
Bit 2: IFC0
0
1
0
1
Description
PLL circuit 1 is not used.
PLL circuit 1 is used.
Description
PLL is not in standby mode.
PLL is in standby mode.
Description
Setting prohibited (do not set)
Description
Setting prohibited (do not set)
1
2
4
1
1/2
1/4
(Initial value)
(Initial value)
(Initial value)
(Initial value)
171
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