HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 388
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 12 Bus State Controller (BSC)
Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT
signal has no effect if asserted in the T1 cycle or the first Tw cycle.
The WAIT signal is sampled at the falling edge of the clock. If the setup time and hold times with
respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge
is used..
However, the WAIT signal is ignored in the following three cases:
• When writing to an external address area using DMA 16-byte transfer in dual address mode
• When transferring data from a DACK-equipped external device to an external address area
• During cache write-back access
Rev.6.00 Mar. 27, 2009 Page 330 of 1036
REJ09B0254-0600
Figure 12.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
using DMA 16-byte transfer in dual address mode
Write
Read
A25 to A0
RD/WR
WAIT
RD
D31 to D0
WEn
D31 to D0
CKIO
BS
CSn
T1
WAITSEL = 1)
Tw
Tw
Wait states inserted
by WAIT signal
Tw
T2
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