M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 108
M306N4FGTFP#U0
Manufacturer Part Number
M306N4FGTFP#U0
Description
MCU 5V 256K T-TEMP PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Specifications of M306N4FGTFP#U0
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M306N4FGTFP#U0M306N4FGTFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 10.6 Interrupt Response Time
Table 10.5 IPL Level that is Set to IPL when Software or Special Interrupt is Accepted
Oscillation stop and re-oscillation detection, Watchdog timer, NMI
Software, Address match, DBC, Single-step
10.5.6 Variation of IPL when Interrupt Request is Accepted
10.5.5 Interrupt Response Time
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 10.5 is set in the IPL. Table 10.5 shows the IPL Level that is Set to IPL when Software or Special
Interrupts is Accepted.
Figure 10.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) on Figure 10.6) and a time during which the interrupt
sequence is executed ((b) on Figure 10.6).
Interrupt Vector Address
Apr 14, 2006
Interrupt request generated
(a) A time from when an interrupt request is generated till when the instruction then
(b) A time during which the interrupt sequence is executed. For details, see the table
Even
Odd
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
page 84 of 376
Interrupt Sources
Instruction
_________
(a)
Interrupt response time
SP Value
Interrupt request acknowledged
Even
Even
Odd
Odd
Interrupt sequence
16-bit Bus, without Wait
(b)
18 cycles
19 cycles
19 cycles
20 cycles
_______
interrupt routine
Instruction in
Value that is Set to IPL
8-bit Bus, without Wait
Not changed
20 cycles
7
Time
10. Interrupts
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