M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 215
M306N4FGTFP#U0
Manufacturer Part Number
M306N4FGTFP#U0
Description
MCU 5V 256K T-TEMP PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Specifications of M306N4FGTFP#U0
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M306N4FGTFP#U0M306N4FGTFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.38 SI/O3 Operation Timing
Figure 15.39 Polarity of Transfer Clock
15.2.1 SI/O3 Operation Timing
15.2.2 CLK Polarity Selection
Figure 15.38 shows the SI/O3 Operation Timing.
The SM34 bit in the S3C register allows selection of the polarity of the transfer clock.
Figure 15.39 shows the Polarity of Transfer Clock.
IR bit in S3IC register
Apr 14, 2006
* This diagram applies to the case where the bits in the S3C register are set as follows:
NOTES:
Signal written to the
SI/O3 internal clock
1. If the SM36 bit = 1 (internal clock), the serial interface starts transmitting or receiving data a maximum of 0.5 to 1.0 transfer clock cycles
2. When the SM36 bit = 1 (internal clock), the SOUT3 pin is placed in the high-impedance state after the transfer finishes.
after writing to the S3TRR register.
S3TRR register
SOUT3 output
SM32 = 0 (SOUT3 output)
SM33 = 1 (SOUT3 output, CLK3 function)
SM34 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
CLK3 output
SIN3 input
(1) When SM34 bit in S3C register = 0
(2) When SM34 bit = 1
*This diagram applies to the case where the bits in the S3C register are set as follows:
NOTES:
CLK3
SOUT3
SIN3
CLK3
SOUT3
SIN3
1. When the SM36 bit = 1 (internal clock), a high level is output from the CLK3 pin if not
2. When the SM36 bit = 1 (internal clock), a low level is output from the CLK3 pin if not
transferring data.
transferring data.
page 191 of 376
"H"
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
"L"
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
1
0
0.5 to 1.0 cycle (max.)
D0
D0
D0
D0
D1
D1
D1
D1
(1)
D0
D2
D2
D2
D2
D1
D3
D3
D3
D3
D2
D4
D4
D4
D4
D3
D5
D5
D5
D5
D6
D6
D6
D6
D4
D7
D7
D7
D7
D5
D6
(NOTE 1)
(NOTE 2)
15. Serial Interface
D7
(NOTE 2)
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