M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 376
M306N4FGTFP#U0
Manufacturer Part Number
M306N4FGTFP#U0
Description
MCU 5V 256K T-TEMP PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Specifications of M306N4FGTFP#U0
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M306N4FGTFP#U0M306N4FGTFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
23.8 Timers
23.8.1 Timer A
23.8.1.1 Timer A (Timer Mode)
23.8.1.2 Timer A (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i =
0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains 0 (count stops) regardless
whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, if the counter is read at the same time it is reloaded, the value FFFFh is read. Also, if the
counter is read before it starts counting after a value is set in the TAi register while not counting, the set
value is read.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to a
high-impedance state.
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF
register, and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
Always make sure the TAiMR register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH, and the
TRGSR register are modified while the TAiS bit remains 0 (count stops) regardless whether after reset or
not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, FFFFh can be read in underflow, while reloading, and 0000h in overflow. When setting the TAi
register to a value during a counter stop, the setting value can be read before a counter starts counting.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to a
high-impedance state.
Apr 14, 2006
page 352 of 376
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23. Usage Notes
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