HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 211
HD64F3048VTF8
Manufacturer Part Number
HD64F3048VTF8
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3048F16.pdf
(907 pages)
Specifications of HD64F3048VTF8
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F3048VX8
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7.3.3
Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in
RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh
cycles are the same as for DRAM (see table 7.4). The state transitions are as shown in figure 7.3.
Pseudo-Static RAM Control Signals: Figure 7.15 shows the control signals for pseudo-static
RAM read, write, and refresh cycles.
Address
bus
CS
RD
HWR
LWR
RFSH
AS
Note:
3
*
Pseudo-Static RAM Refresh Control
16-bit access
Figure 7.15 Pseudo-Static RAM Control Signal Output Timing
Read cycle
Write cycle *
Rev. 7.00 Sep 21, 2005 page 185 of 878
Section 7 Refresh Controller
Area 3 top address
Refresh cycle
REJ09B0259-0700
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