HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 290
HD64F3048VTF8
Manufacturer Part Number
HD64F3048VTF8
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3048F16.pdf
(907 pages)
Specifications of HD64F3048VTF8
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F3048VX8
- Current page: 290 of 907
- Download datasheet (6Mb)
Section 9 I/O Ports
9.3
9.3.1
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 9.2. The pin
functions differ according to the operating mode.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus
output pins (A
in the port 2 data direction register (P2DDR) can designate pins for address bus output (A
or generic input. In mode 7 (single-chip mode), port 2 is a generic input/output port.
When DRAM is connected to area 3, A
write cycles. For details see section 7, Refresh Controller.
Port 2 has software-programmable built-in pull-up MOS. Pins in port 2 can drive one TTL load
and a 90-pF capacitive load. They can also drive a darlington transistor pair.
Rev. 7.00 Sep 21, 2005 page 264 of 878
REJ09B0259-0700
Port 2
Port 2
Overview
15
to A
8
Port 2 pins
). In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Figure 9.2 Port 2 Pin Configuration
Modes 1 to 4
A
A
A
A
A
A
A (output)
A (output)
15
14
13
12
11
10
9
8
9
(output)
(output)
(output)
(output)
(output)
(output)
and A
8
output row and column addresses in read and
Modes 5 and 6
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(output)
Mode 7
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
7
6
5
4
3
2
1
0
15
to A
8
)
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