HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 488

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 13 Serial Communication Interface
Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR.
The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain new transmit data when the MSB is transmitted.
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
Rev. 7.00 Sep 21, 2005 page 462 of 878
REJ09B0259-0700
Bit 4: RE
0
1
Bit 3: MPIE
0
1
Bit 2: TEIE
0
1
and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which
MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,
enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR), and allows the FER and
ORER flags to be set.
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
flags retain their previous values.
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Description
Receiving disabled *
Receiving enabled *
Description
Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clearing conditions]
The MPIE bit is cleared to 0.
MPB = 1 in received data.
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of
the RDRF, FER, and ORER status flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Description
Transmit-end interrupt requests (TEI) are disabled*
Transmit-end interrupt requests (TEI) are enabled*
2
1
(Initial value)
(Initial value)