HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 530
HD64F3048VTF8
Manufacturer Part Number
HD64F3048VTF8
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3048F16.pdf
(907 pages)
Specifications of HD64F3048VTF8
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F3048VX8
- Current page: 530 of 907
- Download datasheet (6Mb)
Section 13 Serial Communication Interface
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the
SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the
level and direction (input or output) of which are determined by DR and DDR bits. This feature
can be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE
bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR
bits should therefore both be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the
TxD pin becomes an output port outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that
clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 13.21.
Rev. 7.00 Sep 21, 2005 page 504 of 878
REJ09B0259-0700
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
0
8 clocks
Start bit
16 clocks
7
15 0
D
0
7
15 0
D
1
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