HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 649
HD6417727BP160CV
Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP160CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
LITEON
Quantity:
46 000
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 Serial Communication Interface with FIFO (SCIF)
Transmitting and Receiving Data (SCIF Initialization): Before transmitting or receiving, clear
the TE and RE bits to 0 in the serial control register 2 (SCSCR2), then initialize the SCIF as
follows.
When changing the communication format, always clear the TE and RE bits to 0 before following
the procedure given below. Clearing TE to 0 initializes the transmit shift register 2 (SCTSR2).
Clearing TE and RE to 0, however, does not initialize the serial status register 2 (SCSSR2),
transmit FIFO data register 2 (SCFTDR2), or receive FIFO data register 2 (SCFRDR2), which
retain their previous contents.
Clear TE to 0 after all transmit data are transmitted and the TEND flag in the SCSSR2 is set. The
transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared
to 0 in transmitting. Set the TFRST bit in the SCFCR2 to 1 and reset the SCFTDR2 before TE is
set again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Rev.6.00 Mar. 27, 2009 Page 591 of 1036
REJ09B0254-0600
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