HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 111
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX),
including modulo addressing, are shown below.
if ( Operation is MOVX.W MOVY.W ) {
have not been updated */
}
else if ( Operation is MOVS.W or MOVS.L ) {
been updated */
updated */
}
ABx=Ax; ABy=Ay;
/* memory access cycle uses ABx and ABy. The addresses to be used
/* Ax is one of R4,R5 */
if ( DMX==0 || DMX==1 && DMY == 1 )} Ax=Ax+(+2 or R8[Ix] or +0);
/* Inc,Index,Not-Update */
else if (! not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );
/* Ay is one of R6,R7 */
if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0); /* Inc,Index,Not-Update */
else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) );
if ( Addressing is Nop, Inc, Add-index-reg ) {
else { /* Decrement, Pre-update */
MAB=As;
/* memory access cycle uses MAB. The address to be used has not
/* As is one of R2 to R5 */
As=As+(+2 or +4 or R8[Is] or +0); /* Inc,Index,Not-Update */
/* As is one of R2 to R5 */
As=As+(-2 or -4);
MAB=As;
/* memory access cycle uses MAB. The address to be used has been
Rev.6.00 Mar. 27, 2009 Page 53 of 1036
REJ09B0254-0600
Section 2 CPU
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