HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 351
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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12.2
12.2.1
Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle
state for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual
reset or by standby mode. Do not access external memory outside area 0 until BCR1 register
initialization is complete.
Note: * Samples the value of the external pin (MD5) designating endian at power-on reset.
Bit 15—Pins A25 to A0 Pull-Up (PULA): Specifies whether or not pins A25 to A0 are pulled up
for 4 cycles immediately after BACK is asserted.
Bit 15: PULA
0
1
Bit 14—Pins D31 to D0 Pull-Up (PULD): Specifies whether or not pins D31 to D0 are pulled up
when not in use.
Bit 14: PULD
0
1
Bit 13—Hi-Z memory control (HIZMEM): Specifies the state of A25 to A0, BS, CS, RD/WR,
WE/DQM, RD, CE2A, CE2B and DRAK0 in standby mode.
Bit 13: HIZMEM
0
1
Initial value:
R/W: R/W
Bit:
BSC Registers
Bus Control Register 1 (BCR1)
PULA PULD HIZ
15
0
R/W
14
0
Description
Not pulled up
Pulled up
Description
Not pulled up (Initial value)
Pulled up
Description
High-impedance state in standby mode.
High in standby mode.
MEM
R/W
13
0
CNT
R/W
HIZ
12
0
ENDI
0/1*
AN
11
R
BST1
R/W
A0
10
0
BST0
R/W
A0
9
0
BST1
R/W
A5
8
0
BST0
Rev.6.00 Mar. 27, 2009 Page 293 of 1036
R/W
A5
7
0
Section 12 Bus State Controller (BSC)
BST1
R/W
A6
6
0
BST0
R/W
A6
5
0
DRAM
R/W
TP2
4
0
DRAM
R/W
TP1
3
0
REJ09B0254-0600
DRAM
R/W
TP0
2
0
(Initial value)
(Initial value)
PCM
R/W
A5
1
0
PCM
R/W
A6
0
0
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