HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 666
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 20 Serial IO (SIOF)
20.2
20.2.1
This register sets the operating mode of SIOF.
This register is initialized by the power on reset or manual reset.
Note: * 0 must be written into these bits. The operation of this LSI is unpredictable when setting
Bits 13 and 4 to 0—Reserved
Bits 15 and 14—Transmit Mode Setting (TRMD1 and TRMD0)
Bit 15: TRMD1
0
1
Note: Refer to section 20.3.3, Transmit Data Format for more details of the functions of each
Bit 12—Receive with Sampling Edge (REDG): TXD_SIO is output at the opposite edge from
the sampling time of RXD_SIO. (see figure 20.4)
Rev.6.00 Mar. 27, 2009 Page 608 of 1036
REJ09B0254-0600
Initial value:
Initial value:
mode.
the value other than 0.
R/W:
R/W:
Register Description
Mode Register (SIMDR)
Bit:
Bit:
TRMD1
TXDIZ
R/W
R/W
15
0
7
0
Bit 14: TRMD0
0
1
0
1
TRMD0
LSBF
R/W
R/W
14
0
6
0
RCIM
R/W
R*
13
Description
Slave mode 1
Slave mode 2
Master mode 1
Master mode 2
—
0
5
0
REDG
R/W
R*
12
—
0
4
0
R/W
FL3
R*
11
—
0
3
0
R/W
FL2
R*
10
—
0
2
0
R/W
FL1
R*
—
9
0
1
0
(Initial value)
R/W
FL0
R*
—
8
0
0
0
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