HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 127

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Table 2.6
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Instruction
MOV
MOV.W @(disp,PC),Rn
MOV.L
MOV
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L
MOV.B Rm,@–Rn
MOV.W Rm,@–Rn
MOV.L
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L
MOV.B Rm,@(R0,Rn)
MOV.W Rm,@(R0,Rn)
MOV.L
#imm,Rn
@(disp,PC),Rn
Rm,Rn
Rm,@Rn
@Rm,Rn
Rm,@–Rn
@Rm+,Rn
Rm,@(disp,Rn)
@(disp,Rm),Rn
Rm,@(R0,Rn)
Data Transfer Instructions
Instruction Code Operation
1110nnnniiiiiiii
1001nnnndddddddd
1101nnnndddddddd
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
0110nnnnmmmm0001
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
0110nnnnmmmm0101
0110nnnnmmmm0110
10000000nnnndddd
10000001nnnndddd
0001nnnnmmmmdddd
10000100mmmmdddd
10000101mmmmdddd
0101nnnnmmmmdddd
0000nnnnmmmm0100
0000nnnnmmmm0101
0000nnnnmmmm0110
imm → Sign extension → Rn –
(disp x 2+PC)→Sign
extension → Rn
(disp x 4+PC)→Rn
Rm→Rn
Rm→(Rn)
Rm→(Rn)
Rm→(Rn)
(Rm)→Sign extension→Rn
(Rm)→Sign extension→Rn
(Rm)→Rn
Rn–1→Rn, Rm→(Rn)
Rn–2→Rn, Rm→(Rn)
Rn–4→Rn, Rm→(Rn)
(Rm)→Sign extension→Rn,
Rm+1→Rm
(Rm)→Sign extension→Rn,
Rm+2→Rm
(Rm)→Rn, Rm+4→Rm
R0→(disp+Rn)
R0→(disp x 2+Rn)
Rm→(disp x 4+Rn)
(disp+Rm)→Sign
extension→R0
(disp x 2+Rm)→Sign
extension→R0
(disp x 4+Rm)→Rn
Rm→(R0+Rn)
Rm→(R0+Rn)
Rm→(R0+Rn)
Privileged
Mode
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Cycles T Bit
1
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Page 67 of 1414
Section 2 CPU
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