HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1460

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Item
17.1 Features
18.1 Features
18.4.2 Serial Operation
Figure 18.4 Example of Transmit
Operation
(Example with 8-Bit Data, Parity,
One Stop Bit)
20.3.10 I
Clock Select Register (ICCKS)
2
C Bus Master Transfer
561
587
621
660
Page Revision (See Manual for Details)
Description amended
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•
•
Description amended
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Figure amended
interrupt request
Table amended
Transmit-FIFO-
Bit
7 to 5
data-empty
TEND
TDFE
Serial
Alarm interrupt (ATI): Frame comparison of
seconds, minutes, hours, date, day of the week,
month, and year can be used as conditions for the
alarm interrupt
Periodic interrupts (PRI): the interrupt cycle may be
1/256 second, 1/64 second, 1/16 second, 1/4
second, 1/2 second, 1 second, or 2 seconds
Carry interrupt (CUI): a carry interrupt indicates
when a carry occurs during a counter read
Six types of interrupts (SCIFIn (n = 0, 1))
(asynchronous mode):
Transmit-data-stop, transmit-FIFO-data-empty,
receive-FIFO-data-full, receive-error (framing
error/parity error), break-receive, and receive-data-
ready interrupts. A common interrupt vector is
assigned to each interrupt source.
Two types of interrupts (SCIFIn (n = 0, 1))
(synchronous mode)
A common interrupt vector is assigned to each
interrupt source.
data
Bit Name
⎯
1
Start
cleared to 0 by Transmit-
bit
0
SCFTDR and TDFE
flag read as 1 then
FIFO-data-empty
interrupt handler
Data written to
D
Initial
Value
All 0
0
D
One frame
1
Data
R/W
R
D
7
Parity
interrupt request
Transmit-FIFO-
bit
0/1
data-empty
Description
Reserved
These bits are always read as 1. The write value
should always be 0.
Stop
bit
1
Start
bit
0
R01UH0083EJ0400 Rev. 4.00
D
0
D
1
Data
D
7
Parity
bit
0/1
Sep 21, 2010
Stop
(mark state)
bit
1
state
Idle
1