HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 230

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Memory Management Unit (MMU)
The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For
more information, see section 5.4, Memory-Mapped Cache.
The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more
information, see section 5.4, Memory-Mapped Cache.
The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For
more information, see section 4.6, Memory-Mapped TLB.
The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more
information, see section 4.6, Memory-Mapped TLB.
The area from H'FC00 0000 to H'FFFF FFFF is reserved for registers of the on-chip peripheral
modules. For more information, see section 37, List of Registers.
(e)
The Uxy area is mapped to the on-chip memory of this LSI. This area is made usable in user mode
when the DSP bit in the SR register is set to 1. In user mode, accessing this area when the DSP bit
is 0 will result in an address error. This area cannot be accessed via the cache and cannot be
address-translated by the TLB. For more information on the Uxy area, see section 6, X/Y
Memory.
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Uxy Area
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'FC00 0000
H'FFFF FFFF
H'E000 0000
Figure 4.4 P4 Area
Cache address array
Control register area
TLB address array
Cache data array
TLB data array
Reserved
Reserved
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010