HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 517

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
The individual clock pulse generator blocks function as follows:
(1)
PLL circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the
CKIO terminal. The multiplication rate is set by the frequency control register. When this is done,
the phase of the leading edge of the internal clock is controlled so that it will agree with the phase
of the leading edge of the CKIO pin.
(2)
PLL circuit 2 quadruples or leaves unchanged the input clock frequency from the crystal oscillator
or EXTAL pin. The multiplication rate is set in the clock operating modes. The clock operating
modes are set by pins MD0, MD1, and MD2. See table 11.2 for more information on clock
operating modes.
(3)
This oscillator is used when a crystal resonator is connected to the XTAL or EXTAL pin. It
operates according to the clock operating mode setting.
(4)
Divider 1 generates a clock at the operating frequency used by the internal or peripheral clock.
The operating frequency of the internal clock (Iφ) can be 1, 1/2, 1/3, or 1/4 times the output
frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin.
The operating frequency of the peripheral clock (Pφ) can be 1, 1/2, 1/3, 1/4, or 1/6 times the output
frequency of PLL circuit 1 within 8.34 MHz ≤ Pφ ≤ 33.34 MHz. The division ratio is set in the
frequency control register.
(5)
The clock frequency control circuit controls the clock frequency using the MD0, MD1, and MD2
pins and the frequency control register.
(6)
The standby control circuit controls the state of the clock pulse generator and other modules
during clock switching or in sleep or standby mode.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
PLL Circuit 1
PLL Circuit 2
Crystal Oscillator
Divider 1
Clock Frequency Control Circuit
Standby Control Circuit
Section 11 Clock Pulse Generator (CPG)
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