HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 738

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Section 20 I
20.7
A stop condition or retransmit start condition should be issued after the falling edge of the ninth
clock is recognized. The falling edge of the ninth clock is recognized by checking the SCLO bit in
the I
A stop condition or retransmit start condition may not be output normally if issuance of a stop or
retransmit start condition is attempted with a certain timing under either of the following cases.
There is no problem in uses under conditions other than the blow.
1. When the rising speed of SCL is lowered due to the load of the SCL line (load capacitance or
2. When the bit synchronous circuit works because the low-level period between the eighth and
Page 678 of 1414
pull-up resistance) exceeding the time defined in section 20.6, Bit Synchronous Circuit.
ninth clock pulses is extended by the slave device.
2
C bus control register 2 (ICCR2).
Usage Notes
2
C Bus Interface (IIC)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010

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