HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 920

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 USB Function Controller (USBF)
(2)
The transmit data register must not write data which is more than maximum packet size. In case of
the transmit data register which has the dual FIFO buffer, the maximum number of data which can
be written in a single time is maximum packet size. Write 1 to TRG/PKTE after data is written.
This writing switches the FIFO buffer. Then, the next data can be written to another buffer.
Therefore data must not be written in both buffers in a single time.
25.9.4
The EP0 interrupt sources assigned to IFR0 (bits 0, 1, and 2) must be assigned to the same
interrupt pins by ISR0. The other interrupt sources have no restrictions.
25.9.5
When the DMA transfer is enabled in endpoint 1, the data register cannot be cleared. Cancel the
DMA transfer before clearing the data register.
25.9.6
The bulk-in transfer has a transfer request interrupt (TR interrupt). The following points should be
noted when using a TR interrupt.
When the IN token is sent from the USB host and there is no data in the corresponding EP FIFO,
the TR interrupt flag is set. However, the TR interrupt is generated continuously at the timing as
shown in figure 20.18. In this case, note that erroneous operation should not occur.
Note: When the IN token is received and there is no data in the corresponding EP FIFO, an NAK
Page 860 of 1414
Transmit Data Register
is determined. However, the TR interrupt flag is set after an NAK handshake is
transmitted. Therefore when the next IN token is received before TRG/PKTE is written,
the TR interrupt flag is set again.
Assigning EP0 Interrupt Sources
FIFO Clear when DMA Transfer is Set
Note on Using TR Interrupt
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010