HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 988
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 26 LCD Controller (LCDC)
26.6
26.6.1
Follow the procedure below to halt access to VRAM for storing display data (synchronous DRAM
in area 3).
• Procedure for Halting Access to Display Data Storage VRAM
This halting procedure is required before selecting self-refreshing for the display data storage
VRAM (synchronous DRAM in area 3) or making a transition to standby mode or module standby
mode.
Page 928 of 1414
A. Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1.
B. Clear the DON bit in LDCNTR to 0 (display-off mode).
C. Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0.
D. Wait for the display time for a single frame to elapse.
Usage Notes
Procedure for Halting Access to Display Data Storage VRAM (Synchronous
DRAM in Area 3)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
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