M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 80
M30835FJGP#U3
Manufacturer Part Number
M30835FJGP#U3
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30835FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
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M
e
E
7.2 Bus Control
. v
J
3
0
2
1
Signals required to access external devices are provided and software wait states are inserted as follows.
The signals are available in memory expansion mode and microprocessor mode only.
7.2.1 Address Bus and Data Bus
7.2.2 Chip-Select Signal
9
C
3 .
B
The address bus is a signal accessing 16M-byte space and uses 24 control pins; A
is the inversed output signal of the highest-order address bit.
The data bus is a signal which inputs and outputs data. The DS register selects the 8-bit data bus from D
to D
BYTE pin, the data bus accessing the external memory space 3 becomes the 8-bit data bus after reset.
When applying an "L" signal to the BYTE pin, the data bus accessing the external memory space 3
becomes the 16-bit data bus.
When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate
state until the microcomputer accesses an external memory space.
When using the DRAMC to access DRAM area, row addresses and column addresses are multiplexed
and output via A
The chip-select signal shares ports with A
determine which CS area is accessed and how many chip-select signals are output. A maximum of four
chip-select signals can be output.
In microprocessor mode, the chip-select signal is not output after reset. A
chip-signal signal.
The chip-select signal becomes "L" while the microcomputer accesses the external CSi area (i=0 to 3). It
becomes high ("H") when the microcomputer accesses another external memory space or an internal
memory space. Figure 7.2 shows an example of the address bus and chip-select signal output.
8 /
0
1
0
3
3
J
G
4
7
a
0 -
n
o r
or the 16-bit data bus from D
3 .
1
u
, 1
3
p
1
2
(
0
M
0
3
6
2
C
8
_____
8 /
to A
Page 55
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20.
M
3
2
C
f o
8 /
4
8
3
8
) T
0
to D
15
0
for each external space. When applying an "H" signal to the
to A
22
and A
_____
23
. The PM11 to PM10 bits in the PM1 register
_____
23
, however, can perform as the
0
______
to A
22
and A
______
23
. A
______
7. Bus
23
0
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