M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 102
M30835FJGP#U5
Manufacturer Part Number
M30835FJGP#U5
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30835FJGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30835FJGP#U5M30835FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3
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2
Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock
0
1
9
C
8.1.4 PLL Clock
3 .
B
8 /
The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be
used as a clock source for the CPU clock or peripheral function clock.
Connect a resistor and capacitor to the V
Set the PD8_6 and PD8_7 bits in the PD8 register to "0" (input mode) and the CM04 bit to "0" (the X
and X
is shown in Figure 8.12. Set the PLV00 bit in the PLV register to "1" (power to PLL).
The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL
frequency synthesizer starts operating. Wait 20 ms (5 V operation) to 50 ms (3.3 V operation) for the PLL
clock to stabilize.
The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or
divided-by-3.
When the PLL clock is used as a clock source for the CPU clock or peripheral function clock, set each bit
as is shown in Table 8.2. Figure 8.13 shows the procedure for using the PLL clock as the CPU clock
source.
To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source). Set the PLC07 bit
in the PLC0 register to "0" (PLL off) and the PLV00 bit to "0" (no power to PLL) before the microcomputer
enters wait or stop mode.
The V
being used, the sub clock cannot be used.
0
1
3
0
3
J
G
4
a
0 -
n
o r
COUT
CONT
3 .
1
u
, 1
3
p
1
2
(
M
pins as ports). After that, connect the V
0
and P8
0
3
6
2
C
8 /
Page 77
6
, 3
pins share pins with X
M
3
2
C
f o
8 /
No
4
3
8
) T
8
(main clock as CPU clock source)
Determine several times whether
Set the MCD register to "08
(main clock does not stop)
the CM23 bit is set to "0"
Set the CM22 bit to "0"
Set the CM21 bit to "0"
(main clock oscillates)
Switch to the
(divide-by-8)
CONT
main clock
CIN
End
and X
Yes
pin when using the PLL frequency synthesizer.
CONT
COUT
16
"
pin, the P8
pins. When the PLL frequency synthesizer is
CM21 to CM23 bits : Bits in CM2 register
6
pin, and the V
8. Clock Generation Circuit
SS
pin to the circuit as
CIN
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