M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 238
M30835FJGP#U5
Manufacturer Part Number
M30835FJGP#U5
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30835FJGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30835FJGP#U5M30835FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
M
e
E
3
. v
J
Table 16.29 Clock-Divided Synchronous Function Select
Figure 16.27 Clock-Divided Synchronous Function
2
0
i=0 to 4
1
9
C
SCLKDIV Bit in
UiSMR Register
3 .
B
8 /
To generate the internal clock synchronized with the external clock, first set the SU1HIM bit in the
UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 16.29.
Then apply a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external
clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register
controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an
external clock operation. Figure 16.27 shows an example of the clock-divided synchronous function.
0
1
3
0
A
B
3
J
G
4
0
0
1
a
Trigger Signal
from the CTSi Pin
External Clock
from the CLKi Pin
0 -
n
o r
3 .
1
TxDi
TxDi
u
Transfer Clock
Transfer Clock
, 1
3
p
1
2
(
i=0 to 4
A, B : See Table 16.29.
M
0
0
3
6
2
C
UiSMR2 Register
Page 213
8 /
SU1HIM Bit in
0 or 1
, 3
0
1
M
3
2
C
f o
8 /
4
1
3
8
) T
8
1
2
Not synchronized
Same division as the external clock
Same division as the external clock
divided by 2
1
2
3
Clock-Divided Synchronous Function
3
4
2
4
5
5
6
3
6
7
7
8
4
8
5
The SCLKSTPB bit in the UiC1 register
stops the clock
16. Serial I/O (Special Function)
6
-
A in Figure 16.27
B in Figure 16.27
Example of Waveform
7
8
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