M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 304
M30835FJGP#U5
Manufacturer Part Number
M30835FJGP#U5
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30835FJGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30835FJGP#U5M30835FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
M
e
E
3
. v
J
2
0
Figure 21.25 Phase-delayed Waveform Output Mode
1
C
9
3 .
B
8 /
0
1
(1) Free-Running Operation
(2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register
3
0
3
J
G
4
a
(The RST2 to RST0 bits in the GiBCR1 register are set to "000
(The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0")
0 -
n
o r
3 .
Base Timer i
OUTCij pin
OUTCij pin
NOTES:
The above diagram applies under the following condition:
Base Timer i
OUTCij pin
PO1jR bit
1
POijR bit
u
, 1
3
p
1
The above diagram applies under the following conditions:
2
2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1"
(
1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and
• The RST2 to RST0 bits in the GiBCR1 register are set to "000
M
0
• The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as initial value). The INV bit is set
• The UD1 to UD0 bits in the G1BCR1 register are set to "00
• m < n+2
0
the IVL bit is set to "0" (output "L" as initial value).
(output "H" as initial value).
the UD1 to UD0 bits to "00
(16-bit waveform generation function).
to "0" (not inversed).
the CAS bit to "0" (16-bit waveform generation function).
3
6
2
C
(1)
(2)
i=0 to 3; j=0 to 7 (however, i=0 when j= 0, 1, 4, 5)
m : Setting value of the GiPOj register (0000
POijR bit: Bits in the IIO0IR to IIO11IR registers
i=0 to 3; j=0 to 7 (however, i=0 when j=1, 4, 5)
m : Setting value of the GiPOj register (0000
n : Setting value of the GiPO0 register (0001
POijR bit: Bits in the IIO0IR to IIO11IR registers
Page 279
8 /
, 3
FFFF
0000
0000
M
n+2
"H"
"L"
"H"
"L"
"1"
"0 "
"H"
"L"
"1"
"0"
16
16
3
16
m
m
2
C
f o
8 /
4
f
3
8
m
BTi
) T
8
2
" (counter increment mode), and the CAS bit to "0"
Inverse
Inverse
Inverse
Write "0" by
program if
setting to "0"
Write "0" by program
if setting to "0"
n+2
f
BTi
65536
f
BTi
16
16
16
to FFFF
to FFFF
to FFFD
21. Intelligent I/O (Waveform Generation Function)
2
Inverse
" (counter increment mode) and
2
" (no base timer reset),
65536X2
n+2
f
16
16
BTi
16
)
)
Inverse
f
Inverse
)
BTi
2
65536
")
f
BTi
Inverse
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