HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 250
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
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Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
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Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
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20 000
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Workarounds: When RAM mode is specified in cache enhanced mode, either of the following
workarounds can be used to avoid the problem.
Workaround 1:
Note: When a break is used to swap instructions by a debugging tool, etc., a memory access
Workaround 2:
Note: The problem still may occur when a break is used to swap instructions by a debugging
Rev. 2.00 Feb. 12, 2010 Page 166 of 1330
REJ09B0554-0200
Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which
address bits [12:0] are identical and only bit [13] differs must not be used. For example,
the 8-Kbyte RAM area from H'7C000000 to H'7C001FFF or from H'7C001000 to
H'7C002FFF may be used.
address may be changed when an instruction following the instruction generating the
break is swapped for another instruction, causing the unused 8-Kbyte RAM area to be
accessed. This will result in the problem described above. However, this phenomenon
only occurs during debugging when a break is used to swap instructions. Using a break
with no instruction swapping will not cause the problem.
Ensure that there are no instructions that generate an interrupt or exception within four
instructions after an instruction that accesses internal RAM. For example, the internal
RAM area can be used as a data table that is accessed only by load instructions, with
writes to the internal RAM area only being performed when the table is generated. It this
case, set SR.BL to 1 to disable interrupts while writing to the table. Also take measures to
ensure that no exceptions due to TLB misses, etc., occur while writing to the table.
tool. This phenomenon only occurs during debugging when a break is used to swap
instructions. Using a break with no instruction swapping will not cause the problem.
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