HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 319
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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9.4
There are four types of interrupt sources: NMI, IRQ, IRL, and peripheral modules. Each interrupt
has a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is
set, the interrupt is masked and interrupt requests are ignored.
9.4.1
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in
SR of the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is
set to 1.
A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1.
Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in ICR is used to select
either rising or falling edge as the detection edge. When the NMIE bit in ICR is modified, the
NMI interrupt is not detected for a maximum of six bus clock cycles after the modification.
NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK3 to
IMASK0) in SR.
9.4.2
IRQ interrupts are input by level at pins IRQ7 to IRQ4. After an IRQ interrupt is accepted, the pin
level must be retained until the interrupt processing starts.
9.4.3
IRL interrupts are input by level at pins IRL3 to IRL0.
The priority level is the level indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000)
indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111)
indicates no interrupt request (interrupt priority level 0). Figure 9.2 shows an example of IRL
interrupt connection, and table 9.6 shows the correspondence between the IRL pins and interrupt
levels.
Interrupt Sources
NMI Interrupt
IRQ Interrupts
IRL Interrupts
Rev. 2.00 Feb. 12, 2010 Page 235 of 1330
REJ09B0554-0200
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