HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 405
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number:
HD6417751RF240V
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Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1
matches the respective counter values.
Bit 0: AF
0
1
Note:
Bits 6, 5, 2, and 1—Reserved. The initial value of these bits is undefined. A write to these bits is
invalid, but the write value should always be 0.
11.2.16 RTC Control Register 2 (RCR2)
RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second
adjustment, and frequency divider RESET and RTC count control.
RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is
undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value
of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value.
Initial value:
*
R/W:
Bit:
Writing 1 does not change the value.
Undefined
PEF
R/W
7
Description
Alarm registers and counter values do not match
[Clearing condition]
When 0 is written to AF
Alarm registers and counter values match*
[Setting condition]
When alarm registers in which the ENB bit is set to 1 and counter values
match*
PES2
R/W
6
0
PES1
R/W
5
0
PES0
R/W
4
0
Rev.4.00 Oct. 10, 2008 Page 305 of 1122
RTCEN
R/W
3
1
ADJ
R/W
11. Realtime Clock (RTC)
2
0
RESET
REJ09B0370-0400
R/W
1
0
(Initial value)
START
R/W
0
1
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