HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 680

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
14.5.4
1. Normal data transfer mode (channel 0)
2. Normal data transfer mode (channel 1 to channel 3)
3. Handshake protocol using the data bus (valid on channel 0 only)
4. Handshake protocol without use of the data bus
5. Direct data transfer mode (valid on channel 2 only)
Rev.4.00 Oct. 10, 2008 Page 580 of 1122
REJ09B0370-0400
Set DTR.ID = 00 and DTR.MD = 00. If a setting of MD = 01, 10, or 11 is made, the DMAC
will halt with an address error. In this case, the error can be cleared by reading DMAOR.AE =
1, then writing AE = 0.
If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored.
a. The handshake protocol using the data bus can be executed only on channel 0. (The DTR
b. If, during execution of the handshake protocol using the data bus for channel 0, a request is
c. If TR only is asserted by means of the handshake protocol without use of the data bus and a
a. With the handshake protocol without use of the data bus, a DMA transfer request can be
b. When using the handshake protocol without use of the data bus, first make the necessary
c. When not using the handshake protocol without use of the data bus, if TR only is asserted
a. If a DMA transfer request for channel 2 is input by simultaneous assertion of DBREQ and
b. In direct data transfer mode (with DBREQ and TR asserted simultaneously), DBREQ is not
format must be set to DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101, 110. Operation is
not guaranteed if the DTR format data settings are DTR.ID = 00, DTR. MD = 00, and
DTR.SZ ≠ 101, 110.)
input for one of channels 1 to 3, and after that DMA transfer is executed settings of
DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101, 110 are input in the handshake protocol
using the data bus, a transfer request will be asserted for channel 0.
DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE =
1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be
cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1.
input to the DMAC again for the channel for which transfer was requested immediately
before by asserting TR only.
settings in the DMAC control registers.
without outputting DTR, a request will be issued for the channel for which DMA transfer
was requested immediately before. Also, if the first DMA transfer request after a power-on
reset is input by asserting TR only, it will be ignored and the DMAC will not operate.
TR during DMA transfer execution with the handshake protocol without use of the data
bus, it will be accepted if there is space in the DDT channel 2 request queue.
interpreted as a bus arbitration signal, and therefore the BAVL signal is never asserted.
Notes on Use of DDT Module