HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 915
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4. If channels A and B both match independently at virtually the same time, and, as a result, the
5. The PCBA or PCBB bit in BRCR is valid for an instruction access break setting.
6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel
7. In the event of contention between a re-execution type exception and a post-execution break in
8. A post-execution break is classified as a completion type exception. Consequently, in the event
e. In the case of an RTE delay slot
f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit
SPC value is the same for both user break interrupts, only one user break interrupt is generated,
but both the CMFA bit and the CMFB bit are set. For example:
110 Instruction (post-execution instruction break on channel A) → SPC = 112, CMFA = 1
112 Instruction (pre-execution instruction break on channel B) → SPC = 112, CMFB = 1
B condition match. For example: A → A → B (user break generated) → B (no break
generated)
a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit
may or may not be set to 1 when the break condition occurs.
of contention between a completion type exception and a post-execution break, the post-
execution break is suppressed in accordance with the priorities of the two events. For example,
The BL bit value before execution of a delay slot instruction is the same as the BL bit value
before execution of an RTE instruction. The BL bit value after execution of a delay slot
instruction is the same as the first BL bit value for the first instruction executed on
returning by means of an RTE instruction (the same as the value of the BL bit in SSR
before execution of the RTE instruction).
before execution of the first instruction of the exception handling routine is 1.
SL.BL
0 → 0
1 → 0
0 → 1
1 → 1
Legend:
A: Accepted
M: Masked
Pre-
Execution
Instruction
Access
A
M
A
M
Post-
Execution
Instruction
Access
A
M
M
M
Pre-
Execution
Instruction
Access
A
M
A
M
Rev.4.00 Oct. 10, 2008 Page 815 of 1122
20. User Break Controller (UBC)
Post-
Execution
Instruction
Access
A
M
M
M
Operand Access
(Address/Data)
A
A
M
M
REJ09B0370-0400
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