SAK-XC866-1FRA AB Infineon Technologies, SAK-XC866-1FRA AB Datasheet
SAK-XC866-1FRA AB
Specifications of SAK-XC866-1FRA AB
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SAK-XC866-1FRA AB Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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XC866 Data Sheet Revision History: Previous Version: V 0.1, 2005-01 V1.0, 2006-02 V1.1, 2006-12 Page Subjects (major changes since last revision) 3 Device summary table is updated for Flash 4-Kb and ROM variants. 13 Footnote is added to MBC pin; ...
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Single-Chip Microcontroller XC800 Family 1 Summary of Features • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers • On-chip memory – ...
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... Synchronous serial channel (SSC) • On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM • PG-TSSOP-38 pin package • Temperature range T A – SAF (- °C) – SAK (-40 to 125 °C) Data Sheet : 2 XC866 Summary of Features V1.2, 2007-10 ...
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... SAK-XC866*-2FRI SAK-XC866*-1FRA SAK-XC866*-1FRI SAF-XC866*-4FRA SAF-XC866*-4FRI SAF-XC866*-2FRA SAF-XC866*-2FRI SAF-XC866*-1FRA SAF-XC866*-1FRI SAK-XC866*-4FRA 3V 3.3 SAK-XC866*-4FRI 3V 3.3 SAK-XC866*-2FRA 3V 3.3 SAK-XC866*-2FRI 3V 3.3 SAK-XC866*-1FRA 3V 3.3 Data Sheet LIN BSL Support No Yes Power P-Flash ...
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... Table 2 Device Summary SAK-XC866*-1FRI 3V 3.3 SAF-XC866*-4FRA 3V 3.3 SAF-XC866*-4FRI 3V 3.3 SAF-XC866*-2FRA 3V 3.3 SAF-XC866*-2FRI 3V 3.3 SAF-XC866*-1FRA 3V 3.3 SAF-XC866*-1FRI 3V 3.3 ROM SAK-XC866*-4RRA SAK-XC866*-4RRI SAK-XC866*-2RRA SAK-XC866*-2RRI SAF-XC866*-4RRA SAF-XC866*-4RRI SAF-XC866*-2RRA SAF-XC866*-2RRI SAK-XC866*-4RRA 3V 3 ...
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... Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the type of delivery For the available ordering codes for the XC866, please refer to your responsible sales representative or your local distributor ...
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General Device Information 2.1 Block Diagram XC866 8-Kbyte 1) Boot ROM 256-byte RAM + 64-byte monitor TMS RAM MBC RESET V 512-byte XRAM DDP V SSP V DDC 4/8/16-Kbyte Flash V SSC or 2) 8/16-Kbyte ROM Clock Generator XTAL1 ...
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Logic Symbol V AREF V AGND RESET MBC TMS XTAL1 XTAL2 Figure 3 XC866 Logic Symbol Data Sheet General Device Information V V DDP SSP XC866 V V DDC SSC 7 XC866 Port 0 6-Bit Port 1 5-Bit Port ...
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Pin Configuration P0.3/SCLK_1/COUT63_1 P0.4/MTSR_1/CC62_1 P0.5/MRST_1/EXINT0_0/COUT62_1 P1.6/CCPOS1_1/T12HR_0/EXINT6 P1.7/CCPOS2_1/T13HR_0 P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1 P0.2/CTRAP_2/TDO_0/TXD_1 P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1 P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0 P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1 P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2 Figure 4 XC866 Pin Configuration, PG-TSSOP-38 Package (top view) Data Sheet MBC XTAL2 5 34 XTAL1 6 33 ...
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Pin Definitions and Functions Table 3 Pin Definitions and Functions Symbol Pin Type Reset Number P0 I/O P0.0 12 P0.1 14 P0.2 13 P0.3 2 P0.4 3 P0.5 4 Data Sheet Function State Port 0 Port ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Number P1 I/O P1.0 27 P1.1 28 P1.5 29 P1.6 9 P1.7 10 Data Sheet Function State Port 1 Port 5-bit bidirectional general purpose I/O port. ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Number P2 I P2.0 15 P2.1 16 P2.2 17 P2.3 20 P2.4 21 P2.5 22 P2.6 23 P2.7 26 Data Sheet Function State Port 2 Port ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Number P3 I P3.0 32 P3.1 33 P3.2 34 P3.3 35 P3.4 36 P3.5 37 P3.6 30 P3.7 31 Data Sheet Function State Port 3 Port ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Number V 18 – DDP V 19 – SSP V 8 – DDC V 7 – SSC V 25 – AREF V 24 – AGND XTAL1 6 I XTAL2 ...
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Functional Description 3.1 Processor Architecture The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC866 ...
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Memory Organization The XC866 CPU operates in the following five address spaces: • 8 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 512 bytes of XRAM memory (XRAM can be read/written as ...
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Figure 7 illustrates the memory address spaces of the XC866-4RR device. F200 H XRAM 512 Bytes F000 H E000 H Boot ROM 8 KBytes C000 H B000 H Flash (4K-X bytes) Total 4 KBytes 2) User ROM (X bytes) A000 ...
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Memory Protection Strategy The XC866 memory protection strategy includes: • Read-out protection: The Flash Memory can be enabled for read-out protection and ROM memory is always protected. • Program and erase protection: The Flash memory in all devices can ...
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Table 5 Flash Protection Type for XC866-2FR and XC866-4FR devices PASSWORD Type of Protection 1XXXXXXX Flash Protection Mode 1 B 0XXXXXXX Flash Protection Mode 0 B For XC866-1FR device and ROM devices: The selection of protection type is summarized in ...
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Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range All registers, except the program counter, reside in the SFR area. The H H SFRs include pointers and ...
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Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of SYSCON0 should not be modified. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared ...
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Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC866 has a 256-SFR address range. However, this is still less than the total number of SFRs ...
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In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access ...
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The page register has the following definition: MOD_PAGE Page Register for module MOD Field Bits PAGE [2:0] STNR [5:4] Data Sheet STNR Type Description rwh Page Bits When written, the ...
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Field Bits OP [7: Data Sheet Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the ...
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Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access to writing of all protected bits, ...
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XC866 Register Overview The SFRs of the XC866 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in of the bitaddressable SFRs appearing in bold typeface. The CPU SFRs can be ...
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Table 7 CPU Register Overview (cont’d) Addr Register Name F0 B Reset Register IP1 Reset Interrupt Priority Register 1 F9 IPH1 Reset Interrupt Priority Register 1 High The system control SFRs can ...
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Table 8 System Control Register Overview (cont’d) Addr Register Name B3 ID Reset Identity Register PMCON0 Reset Power Mode Control Register 0 B5 PMCON1 Reset Power Mode Control Register 1 B6 OSC_CON Reset: ...
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The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 10 Port Register Overview Addr Register Name RMAP = 0 B2 PORT_PAGE Reset Page Register for PORT RMAP = 0, Page 0 80 ...
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Table 10 Port Register Overview (cont’d) Addr Register Name B1 P3_ALTSEL1 Reset Alternate Select 1 Register RMAP = 0, Page 3 80 P0_OD Reset Open Drain Control Register 90 P1_OD Reset ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name CA ADC_RESR0L Reset Result Register 0 Low ADC_RESR0H Reset Result Register 0 High CC ADC_RESR1L Reset Result Register 1 Low CD ADC_RESR1H Reset: 00 ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name CA ADC_CHINFR Reset Channel Interrupt Flag Register CB ADC_CHINCR Reset Channel Interrupt Clear Register CC ADC_CHINSR Reset Channel Interrupt Set Register CD ADC_CHINPR Reset: 00 ...
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Table 12 Timer 2 Register Overview (cont’d) T2_T2MOD Reset Timer 2 Mode Register C2 T2_RC2L Reset Timer 2 Reload/Capture Register Low C3 T2_RC2H Reset Timer 2 Reload/Capture Register High C4 T2_T2L Reset: 00 ...
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Table 13 CCU6 Register Overview (cont’d) Addr Register Name FB CCU6_CC60SRH Reset Capture/Compare Shadow Register for Channel CC60 High FC CCU6_CC61SRL Reset Capture/Compare Shadow Register for Channel CC61 Low FD CCU6_CC61SRH Reset Capture/Compare Shadow ...
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Table 13 CCU6 Register Overview (cont’d) Addr Register Name FD CCU6_CC61RH Reset Capture/Compare Register for Channel CC61 High FE CCU6_CC62RL Reset Capture/Compare Register for Channel CC62 Low FF CCU6_CC62RH Reset Capture/Compare Register for Channel ...
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Table 13 CCU6 Register Overview (cont’d) Addr Register Name FF CCU6_TRPCTRH Reset Trap Control Register High RMAP = 0, Page 3 9A CCU6_MCMOUTL Reset Multi-Channel Mode Output Register Low 9B CCU6_MCMOUTH Reset Multi-Channel Mode ...
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Table 14 SSC Register Overview SSC_CONH Reset Control Register High Programming Mode Operating Mode AC SSC_TBL Reset Transmitter Buffer Register Low AD SSC_RBL Reset Receiver Buffer Register Low AE SSC_BRL Reset ...
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Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not ...
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Table 16 shows the Flash data retention and endurance targets. Table 16 Flash Data Retention and Endurance (Operating Conditions apply) Retention Endurance Program Flash 20 years 1,000 cycles 20 years 1,000 cycles 20 years 1,000 cycles Data Flash 20 years ...
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Sector 2: 128-byte Sector 1: 128-byte Sector 0: 3.75-Kbyte P-Flash Figure 11 Flash Bank Sectorization The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and ...
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Flash Programming Width For the P-Flash banks, a programmed wordline (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must ...
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Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC866 interrupt system provides extended ...
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Timer 0 Overflow Timer 1 Overflow UART Receive UART Transmit EXINT0 EINT0 IRCON0.0 EXINT0 EXICON0.0/1 EXINT1 EINT1 IRCON0.1 EXINT1 EXICON0.2/3 Bit-addressable Request flag is cleared by hardware Figure 14 Interrupt Request Sources (Part 1) Data Sheet TF0 TCON.5 000B ET0 ...
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Timer 2 Overflow T2EX EDGES EL Normal Divider T2MOD.5 Overflow End of EOFSYN Synch Byte FDCON.4 Synch Byte ERRSYN Error FDCON.5 EINT2 EINT3 EXINT3 EXICON0.6/7 EINT4 EXINT4 EXICON1.0/1 EINT5 EXICON1.2/3 EINT6 EXICON1.4/5 Bit-addressable Request flag is cleared by hardware Figure ...
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ADC Service Request 0 ADC Service Request 1 SSC Error SSC Transmit SSC Receive CCU6 Node 0 CCU6 Node 1 CCU6 Node 2 CCU6 Node 3 Bit-addressable Request flag is cleared by hardware Figure 16 Interrupt Request Sources (Part 3) ...
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ICC60R CC60 ISL.0 ICC60F ISL.1 ICC61R CC61 ISL.2 ICC61F ISL.3 ICC62R CC62 ISL.4 ICC62F ISL.5 T12 T12OM One match ISL.6 T12 T12PM Period match ISL.7 T13 T13CM Compare match ISH.0 T13 T13PM Period match ISH.1 TRPF CTRAP ISH.2 Wrong Hall ...
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Interrupt Source and Vector Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an ...
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Table 17 Interrupt Vector Addresses (cont’d) XINTR6 0033 H XINTR7 003B H XINTR8 0043 H XINTR9 004B H XINTR10 0053 H XINTR11 005B H XINTR12 0063 H XINTR13 006B H Data Sheet ADC SSC External Interrupt 2 External Interrupt 3 ...
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Interrupt Priority Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. The NMI has the highest priority and supersedes all other interrupts. Two pairs of interrupt priority registers (IP and ...
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Parallel Ports The XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports ...
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Px_PUDSEL Internal Bus Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 Px_ALTSEL1 Alternate Select Register 1 AltDataOut 3 AltDataOut 2 AltDataOut1 Px_Data Data Register AltDataIn Figure 18 General ...
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Internal Bus AltDataIn AnalogIn Figure 19 General Structure of Input Port Data Sheet Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register enable In Driver Px_DATA Data Register Schmitt Trigger 52 Functional Description VDDP Pull enable Up Device ...
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Power Supply System with Embedded Voltage Regulator The XC866 microcontroller requires two different levels of power supply: • 3 5.0 V for the Embedded Voltage Regulator (EVR) and Ports • 2.5 V for the core, memory, on-chip ...
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Reset Control The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC866 is first powered up, the status of certain pins (see defined to ensure proper ...
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Voltage 5V 2.5V 2.3V 0.9*VDDC Voltage 5V < 0.4V 0V typ. < Figure DDP, DDC The second type of reset in XC866 is the hardware reset. This reset function can be used during normal ...
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Module Reset Behavior Table 19 shows how the functions of the XC866 are affected by the various reset types. A “ ” means that this function is reset to its default state. Table 19 Effect of Reset on Device ...
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Clock Generation Unit The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC866. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. ...
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The clock system provides three ways to generate the system clock: PLL Base Mode The system clock is derived from the VCO base (free running) frequency clock divided by the K factor. Prescaler Mode (VCO Bypass Operation) In VCO bypass ...
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Table 21 System frequency (f Oscillator fosc On-chip 10 MHz External 10 MHz 8 MHz 5 MHz Table 22 shows the VCO range for the XC866. Table 22 VCO Range f f VCOmin VCOmax 150 200 100 150 3.8.1 Recommended ...
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XTAL1 MHz XC866 Oscillator XTAL2 Fundamental Mode Cry s tal Cry s tal Frequenc MHz MHz 10 MHz ...
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Clock Management The CGU generates all clock signals required within the microcontroller from a single clock During normal system operation, the typical frequencies of the different sys modules are as follow: • CPU clock: CCLK, SCLK = ...
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For power saving purposes, the clocks may be disabled or slowed down according to Table 23. Table 23 System frequency (f Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the ...
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Power Saving Modes The power saving modes of the XC866 provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some ...
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Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must ...
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If the WDT is not serviced before the timer overflow, a system malfunction is assumed result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is entered. The prewarning period lasts for 30 (assert WDTRST). The ...
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Table 24 lists the possible watchdog time range that can be achieved for different module clock frequencies . Some numbers are rounded to 3 significant digits. Table 24 Watchdog Time Ranges Reload value Prescaler for f in WDTREL 2 (WDTIN ...
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Universal Asynchronous Receiver/Transmitter The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has ...
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Baud-Rate Generator The baud-rate generator is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock f FDM FDEN f ...
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BG The following formulas calculate the final baud rate without and with the fractional divider respectively: ---------------------------------------------------------------------------------- - where 2 baud rate = BRPRE × ...
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The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Table 27 Deviation Error for UART with Fractional Divider enabled f Prescaling Factor PCLK BRPRE (2 ) 26.67 ...
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Baud Rate Generation using Timer 1 In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it ...
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LIN Protocol The UART can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using ...
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The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of ...
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High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received ...
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Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input ...
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Timer 0 and Timer 1 Timers 0 and 1 are count-up timers which are incremented every machine cycle terms of the input clock, every 2 PCLK cycles. They are fully compatible and can be configured in four ...
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Timer 2 Timer 16-bit general purpose timer (THL2) that has two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled, Timer 2 counts with an input ...
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Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and ...
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The block diagram of the CCU6 module is shown in address decoder T12 clock control start T13 interrupt control Figure 32 CCU6 Block Diagram Data Sheet Figure module kernel compare channel 0 1 dead- channel 1 time 1 control channel ...
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Analog-to-Digital Converter The XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input ...
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ADC Clocking Scheme A common module clock f and digital parts of the ADC module: • input clock for the analog part. ADCA • internal clock for the analog part (defines the time base for ...
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For module clock f = 26.7 MHz, the analog clock f ADC shown in Table 30. Table 30 f Frequency Selection ADCI Module Clock f CTC ADC 26.7 MHz cannot exceed 10 MHz, bit ...
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On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: • use the built-in debug functionality of the XC800 ...
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JTAG Module TMS Primary TCK Debug JTAG TDI Interface TDO Monitor & MBC Bootstrap loader Control line WDT Suspend System Control Unit Reset Clock - parts of OCDS Figure 35 OCDS Block Diagram 3.19.1 JTAG ID Register This is a ...
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Table 31 JTAG ID Summary ROM XC866L-4RR XC866-4RR XC866L-2RR XC866-2RR 3.20 Identification Register The XC866 identity register is located at Page 1 of address B3 ID Identity Register 7 6 PRODID Field Bits VERID [2:0] PRODID [7:3] Data Sheet 1013 ...
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Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the XC866. Note: The electrical parameters are valid for the XC866-4FR and XC866-2FR. The electrical parameters for the ROM variants and XC866-1FR are preliminary, ...
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Absolute Maximum Rating Maximum ratings are the extreme limits to which the XC866 can be subjected to without permanent damage. Table 32 Absolute Maximum Rating Parameters Parameter Ambient temperature Storage temperature Junction temperature Voltage on power supply pin with ...
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... Data Sheet Symbol Limit Values min. V 4.5 DDP V 3.0 DDP 2.3 DDC SYS T -40 A -40 88 Electrical Parameters Unit Notes/ Conditions max. 5 Device 3.6 V 3.3V Device MHz °C 85 SAF-XC866... °C 125 SAK-XC866... / 3. Please refer to SYS V1.2, 2007-10 XC866 Figure 25 ...
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DC Parameters 4.2.1 Input/Output Characteristics Table 34 Input/Output Characteristics (Operating Conditions apply) Parameter Range DDP Output low voltage Output high voltage Input low voltage on port pins (all except P0.0 & P0.1) Input low voltage on ...
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Table 34 Input/Output Characteristics (Operating Conditions apply) Parameter Input low voltage at XTAL1 Input high voltage at XTAL1 Pull-up current Pull-down current 2) Input leakage current Input current at XTAL1 Overload current on any pin Absolute sum of overload currents ...
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Table 34 Input/Output Characteristics (Operating Conditions apply) Parameter V = 3.3V Range DDP Output low voltage Output high voltage Input low voltage on port pins (all except P0.0 & P0.1) Input low voltage on P0.0 & P0.1 Input low voltage ...
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Table 34 Input/Output Characteristics (Operating Conditions apply) Parameter Pull-up current Pull-down current 2) Input leakage current Input current at XTAL1 Overload current on any pin Absolute sum of overload currents Voltage on any pin V during power off DDP Maximum ...
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Not subjected to production test, verified by design/characterization. However, for applications with strict low power-down current requirements mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Data Sheet Electrical ...
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Supply Threshold Characteristics 5.0V VDDP 2.5V VDDC V DDCPOR Figure 36 Supply Threshold Parameters Table 35 Supply Threshold Parameters (Operating Conditions apply) Parameters V prewarning voltage DDC V brownout voltage in DDC 1) active mode RAM data retention voltage ...
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ADC Characteristics The values in the table below are given for an analog power supply between 4 5.5 V. The ADC can be used with an analog power supply down But in this case, ...
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Table 36 ADC Characteristics (Operating Conditions apply; Parameter Symbol Switched C AINSW capacitance at the analog voltage inputs Input resistance of R AREF the reference input Input resistance of R AIN the selected analog channel 1) TUE is tested at ...
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R EXT V C AIN EXT V AREF Figure 37 ADC Input Circuits 4.2.3.1 ADC Conversion Timing Conversion time ADC r = CTC + 2 for CTC = for CTC = 11 ...
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Power Supply Current Table 37 Power Supply Current Parameters (Operating Conditions apply range ) DDP Parameter Range DDP Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled 1) ...
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Table 38 Power Down Current (Operating Conditions apply; Parameter Range DDP 3) Power-Down Mode 1) I The typical values are measured at PDP 2) I The maximum values are measured at PDP 3) I (power-down mode) has ...
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Table 39 Power Supply Current Parameters (Operating Conditions apply 3.3V range) DDP Parameter V = 3.3V Range DDP Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled 1) I The typical values are ...
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Table 40 Power Down Current (Operating Conditions apply; range ) Parameter V = 3.3V Range DDP 3) Power-Down Mode 1) I The typical values are measured at PDP 2) I The maximum values are measured at PDP 3) I (power-down ...
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AC Parameters 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 38, Figure 39 V DDP 90% 10 Figure 38 Rise/Fall Time Parameters V DDP V DDE ...
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Output Rise/Fall Times Table 41 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Range DDP 1) 2) Rise/fall times V = 3.3V Range DDP 1) 2) Rise/fall times 1) Rise/Fall time measurements are taken with 10% ...
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Power-on Reset and PLL Timing Table 42 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Pad operating voltage On-Chip Oscillator start-up time Flash initialization time 1) RESET hold time PLL lock-in in time PLL accumulated jitter 1) RESET ...
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On-Chip Oscillator Characteristics Table 43 On-chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol Nominal frequency f NOM ∆f Long term frequency LT 2) deviation ∆f Short term frequency ST deviation 1) Nominal condition 2 DDC ...
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JTAG Timing Table 44 TCK Clock Timing (Operating Conditions apply; C Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time 0.5 V DDP TCK Figure 43 TCK Clock Timing Data ...
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Table 45 JTAG Timing (Operating Conditions apply; C Parameter TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK TDO high impedance to valid output from TCK TDO valid ...
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SSC Master Mode Timing Table 46 SSC Master Mode Timing (Operating Conditions apply; C Parameter SCLK clock period MTSR delay from SCLK MRST setup to SCLK MRST hold from SCLK 1/f . When f ...
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Package and Reliability 5.1 Package Parameters (PG-TSSOP-38) Table 47 provides the thermal characteristics of the package. Table 47 Thermal Characteristics of the Package Parameter Thermal resistance junction 1) case Thermal resistance junction 1) lead 1) The thermal resistances between ...
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Package Outline Figure 46 PG-TSSOP-38-4 Package Outline Data Sheet Package and Reliability 110 XC866 V1.2, 2007-10 ...
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Quality Declaration Table 48 shows the characteristics of the quality parameters in the XC866. Table 48 Quality Parameters Parameter ESD susceptibility according to Human Body Model (HBM) ESD susceptibility according to Charged Device Model (CDM) pins Data Sheet Symbol ...
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