UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 333
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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9.2 Configuration of Watchdog Timer
WINDOW1 and WINDOW0
The watchdog timer includes the following hardware.
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
of option byte (0080H)
WDCS2 to WDCS0 of
option byte (0080H)
CPU access signal
WDTON of option
Remark For the option byte, refer to CHAPTER 24 OPTION BYTE.
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
f
byte (0080H)
IL
/2
Control register
Setting of Watchdog Timer
controller
Clock
input
Item
Table 9-2. Setting of Option Bytes and Watchdog Timer
Watchdog timer enable
register (WDTE)
Clear, reset control
Figure 9-1. Block Diagram of Watchdog Timer
Table 9-1. Configuration of Watchdog Timer
counter
17-bit
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 9 WATCHDOG TIMER
Watchdog timer enable register (WDTE)
Count clear
signal
2
2
2
7
12
15
/f
/f
/f
error detector
IL
CPU access
IL
IL
to 2
, 2
, 2
Internal bus
14
17
10
/f
/f
/f
IL
IL
IL
,
,
determination
Selector
Window size
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
signal
Configuration
Overflow
signal
Option Byte (0080H)
controller
output
Reset
Internal reset signal
333
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